//In this module: add/sub of val will be executed
//the result of splitted mul will be added

module fpu_s1
#
(
    parameter length_exp=11,
    length_val=52,
    msb_op=length_exp+length_val,
    length_mdiv=2**($clog2(length_val)),
    mdiv_dummy=length_mdiv-length_val
)
(
    input [length_val+2:0]addstage1_base_larger, //1b+val+2b for leading 1 and input rounding
    input [length_val+2:0]addstage1_base_smaller,
    input [length_exp:0]addstage1_exp,
    input fadd_sub,      //perform subtraction in s2
    input [length_mdiv-1:0]mulstage1_LL,
    input [length_mdiv-1:0]mulstage1_LH,
    input [length_mdiv-1:0]mulstage1_HL,
    input [length_mdiv-1:0]mulstage1_HH,
    //outputs
    output [length_val+3:0]fadd_addresult,
    output [2*length_mdiv-1:0]fmul_mulresult



);

//FADD-S2
assign fadd_addresult=addstage1_base_larger+
                        (fadd_sub)?(~addstage1_base_smaller+1):addstage1_base_smaller;


//FMUL-S2
assign fmul_mulresult=({mulstage1_HH,mulstage1_LL}+(mulstage1_HL+mulstage1_LH)<<(length_mdiv/4));

endmodule